/* Generated automatically by the program `genoutput'
from the machine description file `md'.  */

#include "config.h"
#include "rtl.h"
#include "regs.h"
#include "hard-reg-set.h"
#include "real.h"
#include "conditions.h"
#include "insn-flags.h"
#include "insn-config.h"

#ifndef __STDC__
#define const
#endif

#include "output.h"
#include "aux-output.c"

#ifndef INSN_MACHINE_INFO
#define INSN_MACHINE_INFO struct dummy1 {int i;}
#endif


static char *
output_0 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (FP_REG_P (operands[1]))
    return "fmove%.d %f1,%0";
  if (FPA_REG_P (operands[1]))
    abort ();
  return output_move_double (operands);
}
}

static char *
output_1 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  return output_move_double (operands);
}
}

static char *
output_2 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
    return "tst%.l %0";
  /* If you think that the 68020 does not support tstl a0,
     reread page B-167 of the 68020 manual more carefully.  */
  /* On an address reg, cmpw may replace cmpl.  */
  return "cmp%.w %#0,%0";
}
}

static char *
output_3 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
    return "tst%.w %0";
  return "cmp%.w %#0,%0";
}
}

static char *
output_6 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags = CC_IN_68881;
  if (FP_REG_P (operands[0]))
    return "ftst%.x %0";
  return "ftst%.s %0";
}
}

static char *
output_8 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags = CC_IN_68881;
  if (FP_REG_P (operands[0]))
    return "ftst%.x %0";
  return "ftst%.d %0";
}
}

static char *
output_9 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  bsr_seen = 1;
  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
    return "cmpm%.l %1,%0";
  if (REG_P (operands[1])
      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
    { cc_status.flags |= CC_REVERSED;
      return "cmp%.l %d0,%d1";
    }
  return "cmp%.l %d1,%d0";
}
}

static char *
output_10 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
    return "cmpm%.w %1,%0";
  if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
    { cc_status.flags |= CC_REVERSED;
      return "cmp%.w %d0,%d1";
    }
  return "cmp%.w %d1,%d0";
}
}

static char *
output_11 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
    return "cmpm%.b %1,%0";
  if (REG_P (operands[1])
      || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
    { cc_status.flags |= CC_REVERSED;
      return "cmp%.b %d0,%d1";
    }
  return "cmp%.b %d1,%d0";
}
}

static char *
output_13 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags = CC_IN_68881;
  if (REG_P (operands[0]))
    {
      if (REG_P (operands[1]))
        return "fcmp%.x %1,%0";
      else
        return "fcmp%.d %f1,%0";
    }
  cc_status.flags |= CC_REVERSED;
  return "fcmp%.d %f0,%1";
}
}

static char *
output_15 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags = CC_IN_68881;
  if (FP_REG_P (operands[0]))
    {
      if (FP_REG_P (operands[1]))
        return "fcmp%.x %1,%0";
      else
        return "fcmp%.s %f1,%0";
    }
  cc_status.flags |= CC_REVERSED;
  return "fcmp%.s %f0,%1";
}
}

static char *
output_16 (operands, insn)
     rtx *operands;
     rtx insn;
{
 { return output_btst (operands, operands[1], operands[0], insn, 7); }
}

static char *
output_17 (operands, insn)
     rtx *operands;
     rtx insn;
{
 { return output_btst (operands, operands[1], operands[0], insn, 31); }
}

static char *
output_18 (operands, insn)
     rtx *operands;
     rtx insn;
{
 { return output_btst (operands, operands[1], operands[0], insn, 7); }
}

static char *
output_19 (operands, insn)
     rtx *operands;
     rtx insn;
{
 { return output_btst (operands, operands[1], operands[0], insn, 31); }
}

static char *
output_20 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
  return output_btst (operands, operands[1], operands[0], insn, 7);
}
}

static char *
output_21 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == MEM)
    {
      operands[0] = adj_offsettable_operand (operands[0],
                                             INTVAL (operands[1]) / 8);
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
                             7 - INTVAL (operands[1]) % 8);
      return output_btst (operands, operands[1], operands[0], insn, 7);
    }
  operands[1] = gen_rtx (CONST_INT, VOIDmode,
                         15 - INTVAL (operands[1]));
  return output_btst (operands, operands[1], operands[0], insn, 15);
}
}

static char *
output_22 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == MEM)
    {
      operands[0] = adj_offsettable_operand (operands[0],
                                             INTVAL (operands[1]) / 8);
      operands[1] = gen_rtx (CONST_INT, VOIDmode,
                             7 - INTVAL (operands[1]) % 8);
      return output_btst (operands, operands[1], operands[0], insn, 7);
    }
  operands[1] = gen_rtx (CONST_INT, VOIDmode,
                         31 - INTVAL (operands[1]));
  return output_btst (operands, operands[1], operands[0], insn, 31);
}
}

static char *
output_23 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags = CC_Z_IN_NOT_N | CC_NOT_NEGATIVE;
  return "tst%.b %0";
}
}

static char *
output_24 (operands, insn)
     rtx *operands;
     rtx insn;
{

{ register int log = exact_log2 (INTVAL (operands[1]));
  operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
  return output_btst (operands, operands[1], operands[0], insn, 7);
}
}

static char *
output_25 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  extern int flag_slow;
  if (operands[1] == const0_rtx)
    if (TARGET_68020 || flag_slow)
      return "clr%.l %0";
  return "pea %a1%.w";
}
}

static char *
output_26 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (ADDRESS_REG_P (operands[0]))
    return "sub%.l %0,%0";
  if (!TARGET_68020 && DATA_REG_P (operands[0]))
    return "moveq%.l #0,%0";
  return "clr%.l %0";
}
}

static char *
output_27 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  return "move%.l %1,%2";
}

}

static char *
output_28 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  bsr_seen = 0;
  return "lea %a1,%0";
}
}

static char *
output_30 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (which_alternative == 3)
    abort ();
  if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
    abort ();
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      if (DATA_REG_P (operands[0]) && INTVAL (operands[1]) < 0x8000
                                   && INTVAL (operands[1]) >= -0x8000)
         REG_INIT_DBRA (operands[0]) = 1;
      if (operands[1] == const0_rtx
          && GET_CODE (operands[0]) == MEM
          && (!TARGET_68020 && !MEM_VOLATILE_P (operands[0])))
        return "clr%.l %0";
      else if (DATA_REG_P (operands[0])
               && INTVAL (operands[1]) < 128
               && INTVAL (operands[1]) >= -128)
        return "moveq%.l %1,%0";
#ifndef NO_ADDSUB_Q
      else if (DATA_REG_P (operands[0])
               /* Do this with a moveq #N-8, dreg; addq #8,dreg */
               && INTVAL (operands[1]) < 136
               && INTVAL (operands[1]) >= 128)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
          return "moveq%.l %1,%0\n\taddq%.w %#8,%0";
        }
      else if (DATA_REG_P (operands[0])
               /* Do this with a moveq #N+8, dreg; subq #8,dreg */
               && INTVAL (operands[1]) < -128
               && INTVAL (operands[1]) >= -136)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8);
          return "moveq%.l %1,%0\n\tsubq%.w %#8,%0";
        }
#endif
      else if (DATA_REG_P (operands[0])
               /* If N is in the right range and is even, then use
                  moveq #N/2, dreg; addl dreg,dreg */
               && INTVAL (operands[1]) > 127
               && INTVAL (operands[1]) <= 254
               && INTVAL (operands[1]) % 2 == 0)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2);
          return "moveq%.l %1,%0\n\tadd%.w %0,%0";
        }
      else if (ADDRESS_REG_P (operands[0])
               && INTVAL (operands[1]) < 0x8000
               && INTVAL (operands[1]) >= -0x8000)
       {
        if (operands[1] == const0_rtx)
          return "sub%.l %0,%0";
        return "move%.w %1,%0";
       }
      else if (push_operand (operands[0], SImode)
               && INTVAL (operands[1]) < 0x8000
               && INTVAL (operands[1]) >= -0x8000)
        return "pea %a1%.w";
    }
  else if ((GET_CODE (operands[1]) == SYMBOL_REF
            || GET_CODE (operands[1]) == CONST)
           && push_operand (operands[0], SImode))
    {
      bsr_seen = 0;
      if (plus_symbol_ref_p (operands[1]) == 1)
        return "pea %a1%.w";
      else
        return "pea %a1";
    }
  else if ((GET_CODE (operands[1]) == SYMBOL_REF
            || GET_CODE (operands[1]) == CONST)
           && ADDRESS_REG_P (operands[0]))
   {
     bsr_seen = 0;
     if (plus_symbol_ref_p (operands[1]) == 1)
       return "lea %a1%.w,%0";
     else
       return "lea %a1,%0";
   }
  return "move%.l %1,%0";
}
}

static char *
output_31 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  return "move%.w %1,%2";
}

}

static char *
output_32 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      if (operands[1] == const0_rtx
          && (DATA_REG_P (operands[0])
              || GET_CODE (operands[0]) == MEM)
          && !(GET_CODE (operands[0]) == MEM
               && (!TARGET_68020 && MEM_VOLATILE_P (operands[0]))))
        return "clr%.w %0";
      else if (DATA_REG_P (operands[0])
               && INTVAL (operands[1]) < 128
               && INTVAL (operands[1]) >= -128)
        return "moveq%.l %1,%0";
      else if (INTVAL (operands[1]) < 0x8000
               && INTVAL (operands[1]) >= -0x8000)
        return "move%.w %1,%0";
    }
  else if (CONSTANT_P (operands[1]))
    return "move%.l %1,%0";

  /* Recognize the insn before a tablejump, one that refers
     to a table of offsets.  Such an insn will need to refer
     to a label on the insn.  So output one.  Use the label-number
     of the table of offsets to generate this label.  */
  if (GET_CODE (operands[1]) == MEM
      && GET_CODE (XEXP (operands[1], 0)) == PLUS
      && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
          || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
    {
      rtx labelref;
      if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
        labelref = XEXP (XEXP (operands[1], 0), 0);
      else
        labelref = XEXP (XEXP (operands[1], 0), 1);
      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, "?I",
                                 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
      /* For sake of 3b1, set flag saying we need to define the symbol
         LD%n (with value L%n-LI%n) at the end of the switch table.  */
      RTX_INTEGRATED_P (next_real_insn (XEXP (labelref, 0))) = 1;
    }
  return "move%.w %1,%0";
}
}

static char *
output_33 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      if (operands[1] == const0_rtx
          && (DATA_REG_P (operands[0])
              || GET_CODE (operands[0]) == MEM)
          && !(GET_CODE (operands[0]) == MEM
               && (!TARGET_68020  && MEM_VOLATILE_P (operands[0]))))
        return "clr%.w %0";
    }
  return "move%.w %1,%0";
}
}

static char *
output_34 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  return "move%.b %1,%2";
}

}

static char *
output_35 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[4];

  /* This is probably useless, since it loses for pushing a struct
     of several bytes a byte at a time.  */
  if (GET_CODE (operands[0]) == MEM
      && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
      && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
    {
      xoperands[1] = operands[1];
      xoperands[2]
        = gen_rtx (MEM, QImode,
                   gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
      /* Just pushing a byte puts it in the high byte of the halfword.  */
      /* We must put it in the low-order, high-numbered byte.  */
      output_asm_insn ("move%.b %1,%-\n\tmove%.b %@,%2", xoperands);
      return "";
    }

  /* Moving a byte into an address register is not possible.  */
  /* Use d0 as an intermediate, but don't clobber its contents.  */
  if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
    {
      /* ??? For 2.5, don't allow this choice and use secondary reloads
         instead.

         See if the address register is used in the address.  If it
         is, we have to generate a more complex sequence than those below.  */
      if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
                             operands[1], NULL_RTX))
        {
          /* See if the stack pointer is used in the address.  If it isn't,
             we can push d0 or d1 (the insn can't use both of them) on
             the stack, perform our move into d0/d1, copy the byte from d0/1,
             and pop d0/1.  */
          if (! reg_mentioned_p (stack_pointer_rtx, operands[1]))
            {
              if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
                return "move%.l d0,%-\n\tmove%.b %1,d0\n\tmove%.l d0,%0\n\tmove%.l %+,d0";
              else
                return "move%.l d1,%-\n\tmove%.b %1,d1\n\tmove%.l d1,%0\n\tmove%.l %+,d1";
            }
          else
            {
              /* Otherwise, we know that d0 cannot be used in the address
                 (since sp and one address register is).  Assume that sp is
                 being used as a base register and replace the address
                 register that is our operand[0] with d0.  */
              rtx reg_map[FIRST_PSEUDO_REGISTER];
              int i;

              for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
                reg_map[i] = 0;

              reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0);
              operands[1] = copy_rtx (operands[1]);
              replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0);
              return "exg d0,%0\n\tmove%.b %1,d0\n\texg d0,%0";
            }
        }

      /* If the address of operand 1 uses d0, choose d1 as intermediate.  */
      if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
        return "exg d1,%0\n\tmove%.b %1,d1\n\texg d1,%0";
      /* Otherwise d0 is usable.
         (An effective address on the 68k can't use two d-regs.)  */
      else
        return "exg d0,%0\n\tmove%.b %1,d0\n\texg d0,%0";
    }

  /* Likewise for moving from an address reg.  */
  if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
    {
      /* ??? For 2.5, don't allow this choice and use secondary reloads
         instead.

         See if the address register is used in the address.  If it
         is, we have to generate a more complex sequence than those below.  */
      if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1,
                             operands[0], NULL_RTX))
        {
          /* See if the stack pointer is used in the address.  If it isn't,
             we can push d0 or d1 (the insn can't use both of them) on
             the stack, copy the byte to d0/1, perform our move from d0/d1,
             and pop d0/1.  */
          if (! reg_mentioned_p (stack_pointer_rtx, operands[0]))
            {
              if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
                return "move%.l d0,%-\n\tmove%.l %1,d0\n\tmove%.b d0,%0\n\tmove%.l %+,d0";
              else
                return "move%.l d1,%-\n\tmove%.l %1,d1\n\tmove%.b d1,%0\n\tmove%.l %+,d1";
            }
          else
            {
              /* Otherwise, we know that d0 cannot be used in the address
                 (since sp and one address register is).  Assume that sp is
                 being used as a base register and replace the address
                 register that is our operand[1] with d0.  */
              rtx reg_map[FIRST_PSEUDO_REGISTER];
              int i;

              for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
                reg_map[i] = 0;

              reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0);
              operands[0] = copy_rtx (operands[0]);
              replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0);
              return "exg d0,%1\n\tmove%.b d0,%0\n\texg d0,%1";
            }
        }

      if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
        return "exg d1,%1\n\tmove%.b d1,%0\n\texg d1,%1";
      else
        return "exg d0,%1\n\tmove%.b d0,%0\n\texg d0,%1";
    }

  if (operands[1] == const0_rtx
      && !(!TARGET_68020 && GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
    return "clr%.b %0";
  if (GET_CODE (operands[1]) == CONST_INT
      && INTVAL (operands[1]) == -1
      && !(!TARGET_68020 && GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
    {
      CC_STATUS_INIT;
      return "st %0";
    }
  if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
    return "move%.l %1,%0";
  if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
    return "move%.w %1,%0";
  return "move%.b %1,%0";
}
}

static char *
output_36 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const0_rtx
      && !(!TARGET_68020 && GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
    return "clr%.b %0";
  return "move%.b %1,%0";
}
}

static char *
output_37 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (which_alternative >= 4)
    abort ();
  if (FPA_REG_P (operands[0]))
    abort ();
  if (FPA_REG_P (operands[1]))
    abort ();
  if (FP_REG_P (operands[0]))
    {
      if (FP_REG_P (operands[1]))
        return "fmove%.x %1,%0";
      else if (ADDRESS_REG_P (operands[1]))
        return "move%.l %1,%-\n\tfmove%.s %+,%0";
      else if (GET_CODE (operands[1]) == CONST_DOUBLE)
        return output_move_const_single (operands);
      return "fmove%.s %f1,%0";
    }
  if (FP_REG_P (operands[1]))
    {
      if (ADDRESS_REG_P (operands[0]))
        return "fmove%.s %1,%-\n\tmove%.l %+,%0";
      return "fmove%.s %f1,%0";
    }
  return "move%.l %1,%0";
}
}

static char *
output_38 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (which_alternative == 6)
    abort ();
  if (FPA_REG_P (operands[0]))
    abort ();
  else if (FPA_REG_P (operands[1]))
    abort ();
  if (FP_REG_P (operands[0]))
    {
      if (FP_REG_P (operands[1]))
        return "fmove%.x %1,%0";
      if (REG_P (operands[1]))
        {
          rtx xoperands[2];
          xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
          output_asm_insn ("move%.l %1,%-", xoperands);
          output_asm_insn ("move%.l %1,%-", operands);
          return "fmove%.d %+,%0";
        }
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
        return output_move_const_double (operands);
      return "fmove%.d %f1,%0";
    }
  else if (FP_REG_P (operands[1]))
    {
      if (REG_P (operands[0]))
        {
          output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands);
          operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
          return "move%.l %+,%0";
        }
      else
        return "fmove%.d %f1,%0";
    }
  return output_move_double (operands);
}

}

static char *
output_39 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (which_alternative == 8)
    abort ();
  if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
    abort ();
  if (FP_REG_P (operands[0]))
    {
      if (FP_REG_P (operands[1]))
        return "fmove%.x %1,%0";
      if (REG_P (operands[1]))
        {
          rtx xoperands[2];
          xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
          output_asm_insn ("move%.l %1,%-", xoperands);
          output_asm_insn ("move%.l %1,%-", operands);
          return "fmove%.d %+,%0";
        }
      if (GET_CODE (operands[1]) == CONST_DOUBLE)
        return output_move_const_double (operands);
      return "fmove%.d %f1,%0";
    }
  else if (FP_REG_P (operands[1]))
    {
      if (REG_P (operands[0]))
        {
          output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands);
          operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
          return "move%.l %+,%0";
        }
      else
        return "fmove%.d %f1,%0";
    }
  return output_move_double (operands);
}

}

static char *
output_41 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (plus_symbol_ref_p (operands[1]) == 1)
    return "lea %a1%.w,%0";
  else
    return "lea %a1,%0";
}
}

static char *
output_42 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == REG)
    {
      /* Must clear condition codes, since the mov.l bases them on
         the entire 32 bits, not just the desired 8 bits.  */
      CC_STATUS_INIT;
      return "move%.l %1,%0";
    }
  if (GET_CODE (operands[1]) == MEM)
    operands[1] = adj_offsettable_operand (operands[1], 3);
  return "move%.b %1,%0";
}
}

static char *
output_43 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == REG
      && (GET_CODE (operands[1]) == MEM
          || GET_CODE (operands[1]) == CONST_INT))
    {
      /* Must clear condition codes, since the mov.w bases them on
         the entire 16 bits, not just the desired 8 bits.  */
      CC_STATUS_INIT;
      return "move%.w %1,%0";
    }
  if (GET_CODE (operands[0]) == REG)
    {
      /* Must clear condition codes, since the mov.l bases them on
         the entire 32 bits, not just the desired 8 bits.  */
      CC_STATUS_INIT;
      return "move%.l %1,%0";
    }
  if (GET_CODE (operands[1]) == MEM)
    operands[1] = adj_offsettable_operand (operands[1], 1);
  return "move%.b %1,%0";
}
}

static char *
output_44 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[0]) == REG)
    {
      /* Must clear condition codes, since the mov.l bases them on
         the entire 32 bits, not just the desired 8 bits.  */
      CC_STATUS_INIT;
      return "move%.l %1,%0";
    }
  if (GET_CODE (operands[1]) == MEM)
    operands[1] = adj_offsettable_operand (operands[1], 2);
  return "move%.w %1,%0";
}
}

static char *
output_48 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (DATA_REG_P (operands[0]))
    {
      if (GET_CODE (operands[1]) == REG
          && REGNO (operands[0]) == REGNO (operands[1]))
        return "and%.l %#$ffff,%0";
      if (reg_mentioned_p (operands[0], operands[1]))
        return "move%.w %1,%0\n\tand%.l %#$ffff,%0";
      return "clr%.l %0\n\tmove%.w %1,%0";
    }
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
    return "move%.w %1,%0\n\tclr%.w %0";
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
    return "clr%.w %0\n\tmove%.w %1,%0";
  else
    {
      output_asm_insn ("clr%.w %0", operands);
      operands[0] = adj_offsettable_operand (operands[0], 2);
      return "move%.w %1,%0";
    }
}
}

static char *
output_49 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (DATA_REG_P (operands[0]))
    {
      if (GET_CODE (operands[1]) == REG
          && REGNO (operands[0]) == REGNO (operands[1]))
        return "and%.w %#$ff,%0";
      if (reg_mentioned_p (operands[0], operands[1]))
        return "move%.b %1,%0\n\tand%.w %#$ff,%0";
      return "clr%.w %0\n\tmove%.b %1,%0";
    }
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
    {
      if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM)
        {
          output_asm_insn ("clr%.w %-", operands);
          operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
                                 plus_constant (stack_pointer_rtx, 1));
          return "move%.b %1,%0";
        }
      else
        return "move%.b %1,%0\n\tclr%.b %0";
    }
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
    return "clr%.b %0\n\tmove%.b %1,%0";
  else
    {
      output_asm_insn ("clr%.b %0", operands);
      operands[0] = adj_offsettable_operand (operands[0], 1);
      return "move%.b %1,%0";
    }
}
}

static char *
output_50 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (DATA_REG_P (operands[0]))
    {
      if (GET_CODE (operands[1]) == REG
          && REGNO (operands[0]) == REGNO (operands[1]))
        return "and%.l %#$ff,%0";
      if (reg_mentioned_p (operands[0], operands[1]))
        return "move%.b %1,%0\n\tand%.l %#$ff,%0";
      return "clr%.l %0\n\tmove%.b %1,%0";
    }
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
    {
      operands[0] = XEXP (XEXP (operands[0], 0), 0);
      return "clr.l -(%0)\n\tmove%.b %1,3(%0)";
    }
  else if (GET_CODE (operands[0]) == MEM
           && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
    {
      operands[0] = XEXP (XEXP (operands[0], 0), 0);
      return "clr.l (%0)+\n\tmove%.b %1,-1(%0)";
    }
  else
    {
      output_asm_insn ("clr%.l %0", operands);
      operands[0] = adj_offsettable_operand (operands[0], 3);
      return "move%.b %1,%0";
    }
}
}

static char *
output_51 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (ADDRESS_REG_P (operands[0]))
    return "move%.w %1,%0";
  return "ext%.l %0";
}
}

static char *
output_55 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
    {
      if (REGNO (operands[0]) == REGNO (operands[1]))
        {
          /* Extending float to double in an fp-reg is a no-op.
             NOTICE_UPDATE_CC has already assumed that the
             cc will be set.  So cancel what it did.  */
          cc_status = cc_prev_status;
          return "";
        }
      return "fmove%.x %1,%0";
    }
  if (FP_REG_P (operands[0]))
    return "fmove%.s %f1,%0";
  if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
    {
      output_asm_insn ("fmove%.d %f1,%-\n\tmove%.l %+,%0", operands);
      operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
      return "move%.l %+,%0";
    }
  return "fmove%.d %f1,%0";
}
}

static char *
output_66 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (FP_REG_P (operands[1]))
    return "fintrz%.x %f1,%0";
  return "fintrz%.d %f1,%0";
}
}

static char *
output_67 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (FP_REG_P (operands[1]))
    return "fintrz%.x %f1,%0";
  return "fintrz%.s %f1,%0";
}
}

static char *
output_75 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (! operands_match_p (operands[0], operands[1]))
    {
      if (!ADDRESS_REG_P (operands[1]))
        {
          rtx tmp = operands[1];

          operands[1] = operands[2];
          operands[2] = tmp;
        }
      /* These insns can result from reloads to access
         stack slots over 64k from the frame pointer.  */
      if (GET_CODE (operands[2]) == CONST_INT
          && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
        return "move%.l %2,%0\n\tadd%.l %1,%0";
      if (GET_CODE (operands[2]) == REG)
        return "lea (%1,%2.l),%0";
      else
        return TARGET_68020 ? "lea (%c2,%1),%0"
                            : "lea %c2(%1),%0";
    }
  if (GET_CODE (operands[2]) == CONST_INT)
    {
#ifndef NO_ADDSUB_Q
      if (INTVAL (operands[2]) > 0
          && INTVAL (operands[2]) <= 8)
        return (ADDRESS_REG_P (operands[0])
                ? "addq%.w %2,%0"
                : "addq%.l %2,%0");
      if (INTVAL (operands[2]) < 0
          && INTVAL (operands[2]) >= -8)
        {
          operands[2] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[2]));
          return (ADDRESS_REG_P (operands[0])
                  ? "subq%.w %2,%0"
                  : "subq%.l %2,%0");
        }
#endif
      if (ADDRESS_REG_P (operands[0])
          && INTVAL (operands[2]) >= -0x8000
          && INTVAL (operands[2]) < 0x8000)
        return TARGET_68020 ? "lea (%c2,%0),%0"
                            : "lea %c2(%0),%0";
    }
  return "add%.l %2,%0";
}
}

static char *
output_77 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      /* If the constant would be a negative number when interpreted as
         HImode, make it negative.  This is usually, but not always, done
         elsewhere in the compiler.  First check for constants out of range,
         which could confuse us.  */

      if (INTVAL (operands[2]) >= 32768)
        operands[2] = gen_rtx (CONST_INT, VOIDmode,
                               (short)INTVAL (operands[2]));

      if (INTVAL (operands[2]) > 0
          && INTVAL (operands[2]) <= 8)
        return "addq%.w %2,%0";
      if (INTVAL (operands[2]) < 0
          && INTVAL (operands[2]) >= -8)
        {
          operands[2] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[2]));
          return "subq%.w %2,%0";
        }
      /* On everything except the 68000 it is faster to use two
         addqw instructions to add a small integer (8 < N <= 16)
         to an address register.  Likewise for subqw. */
      if (INTVAL (operands[2]) > 8
          && INTVAL (operands[2]) <= 16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
          return "addq%.w %#8,%0\n\taddq%.w %2,%0";
        }
      if (INTVAL (operands[2]) < -8
          && INTVAL (operands[2]) >= -16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[2] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[2]) - 8);
          return "subq%.w %#8,%0\n\tsubq%.w %2,%0";
        }
    }
#endif
  return "add%.w %2,%0";
}
}

static char *
output_78 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      /* If the constant would be a negative number when interpreted as
         HImode, make it negative.  This is usually, but not always, done
         elsewhere in the compiler.  First check for constants out of range,
         which could confuse us.  */

      if (INTVAL (operands[1]) >= 32768)
        operands[1] = gen_rtx (CONST_INT, VOIDmode,
                               (short)INTVAL (operands[1]));

      if (INTVAL (operands[1]) > 0
          && INTVAL (operands[1]) <= 8)
        return "addq%.w %1,%0";
      if (INTVAL (operands[1]) < 0
          && INTVAL (operands[1]) >= -8)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[1]));
          return "subq%.w %1,%0";
        }
      /* On everything except the 68000 it is faster to use two
         addqw instructions to add a small integer (8 < N <= 16)
         to an address register.  Likewise for subqw. */
      if (INTVAL (operands[1]) > 8
          && INTVAL (operands[1]) <= 16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
          return "addq%.w %#8,%0\n\taddq%.w %1,%0";
        }
      if (INTVAL (operands[1]) < -8
          && INTVAL (operands[1]) >= -16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[1]) - 8);
          return "subq%.w %#8,%0\n\tsubq%.w %1,%0";
        }
    }
#endif
  return "add%.w %1,%0";
}
}

static char *
output_79 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      /* If the constant would be a negative number when interpreted as
         HImode, make it negative.  This is usually, but not always, done
         elsewhere in the compiler.  First check for constants out of range,
         which could confuse us.  */

      if (INTVAL (operands[1]) >= 32768)
        operands[1] = gen_rtx (CONST_INT, VOIDmode,
                               (short)INTVAL (operands[1]));

      if (INTVAL (operands[1]) > 0
          && INTVAL (operands[1]) <= 8)
        return "addq%.w %1,%0";
      if (INTVAL (operands[1]) < 0
          && INTVAL (operands[1]) >= -8)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[1]));
          return "subq%.w %1,%0";
        }
      /* On everything except the 68000 it is faster to use two
         addqw instructions to add a small integer (8 < N <= 16)
         to an address register.  Likewise for subqw. */
      if (INTVAL (operands[1]) > 8
          && INTVAL (operands[1]) <= 16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
          return "addq%.w %#8,%0\n\taddq%.w %1,%0";
        }
      if (INTVAL (operands[1]) < -8
          && INTVAL (operands[1]) >= -16
          && ADDRESS_REG_P (operands[0])
          && TARGET_68020)
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode,
                                 - INTVAL (operands[1]) - 8);
          return "subq%.w %#8,%0\n\tsubq%.w %1,%0";
        }
    }
#endif
  return "add%.w %1,%0";
}
}

static char *
output_80 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[2]) == CONST_INT)
    {
      if (INTVAL (operands[2]) >= 128)
        operands[2] = gen_rtx (CONST_INT, VOIDmode,
                               (char)INTVAL (operands[2]));

      if (INTVAL (operands[2]) > 0
          && INTVAL (operands[2]) <= 8)
        return "addq%.b %2,%0";
      if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
       {
         operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
         return "subq%.b %2,%0";
       }
    }
#endif
  return "add%.b %2,%0";
}
}

static char *
output_81 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      if (INTVAL (operands[1]) >= 128)
        operands[1] = gen_rtx (CONST_INT, VOIDmode,
                               (char)INTVAL (operands[1]));

      if (INTVAL (operands[1]) > 0
          && INTVAL (operands[1]) <= 8)
        return "addq%.b %1,%0";
      if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
       {
         operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
         return "subq%.b %1,%0";
       }
    }
#endif
  return "add%.b %1,%0";
}
}

static char *
output_82 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#ifndef NO_ADDSUB_Q
  if (GET_CODE (operands[1]) == CONST_INT)
    {
      if (INTVAL (operands[1]) >= 128)
        operands[1] = gen_rtx (CONST_INT, VOIDmode,
                               (char)INTVAL (operands[1]));

      if (INTVAL (operands[1]) > 0
          && INTVAL (operands[1]) <= 8)
        return "addq%.b %1,%0";
      if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
       {
         operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]));
         return "subq%.b %1,%0";
       }
    }
#endif
  return "add%.b %1,%0";
}
}

static char *
output_84 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]))
    return "fadd%.x %2,%0";
  return "fadd%.d %f2,%0";
}
}

static char *
output_86 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
    return "fadd%.x %2,%0";
  return "fadd%.s %f2,%0";
}
}

static char *
output_87 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (! operands_match_p (operands[0], operands[1]))
    {
      if (operands_match_p (operands[0], operands[2]))
        {
#ifndef NO_ADDSUB_Q
          if (GET_CODE (operands[1]) == CONST_INT)
            {
              if (INTVAL (operands[1]) > 0
                  && INTVAL (operands[1]) <= 8)
                return "subq%.l %1,%0\n\tneg%.l %0";
            }
#endif
          return "sub%.l %1,%0\n\tneg%.l %0";
        }
      /* This case is matched by J, but negating -0x8000
         in an lea would give an invalid displacement.
         So do this specially.  */
      if (INTVAL (operands[2]) == -0x8000)
        return "move%.l %1,%0\n\tsub%.l %2,%0";
        return TARGET_68020 ? "lea (%n2,%1),%0"
                            : "lea %n2(%1),%0";
    }
  if (GET_CODE (operands[2]) == CONST_INT)
    {
#ifndef NO_ADDSUB_Q
      if (INTVAL (operands[2]) > 0
          && INTVAL (operands[2]) <= 8)
        return "subq%.l %2,%0";
#endif
      if (ADDRESS_REG_P (operands[0])
          && INTVAL (operands[2]) >= -0x8000
          && INTVAL (operands[2]) < 0x8000)
        return "sub%.w %2,%0";
    }
  return "sub%.l %2,%0";
}
}

static char *
output_94 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]))
    return "fsub%.x %2,%0";
  return "fsub%.d %f2,%0";
}
}

static char *
output_96 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
    return "fsub%.x %2,%0";
  return "fsub%.s %f2,%0";
}
}

static char *
output_104 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]))
    return "fmul%.x %2,%0";
  return "fmul%.d %f2,%0";
}
}

static char *
output_106 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
    return "fsglmul%.x %2,%0";
  return "fsglmul%.s %f2,%0";
}
}

static char *
output_114 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]))
    return "fdiv%.x %2,%0";
  return "fdiv%.d %f2,%0";
}
}

static char *
output_116 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
    return "fsgldiv%.x %2,%0";
  return "fsgldiv%.s %f2,%0";
}
}

static char *
output_117 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  /* The swap insn produces cc's that don't correspond to the result.  */
  CC_STATUS_INIT;
  return "ext.l %0\n\tdivs%.w %2,%0\n\tswap %0";
}
}

static char *
output_118 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  /* The swap insn produces cc's that don't correspond to the result.  */
  CC_STATUS_INIT;
  return "divs%.w %2,%0\n\tswap %0";
}
}

static char *
output_119 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  /* The swap insn produces cc's that don't correspond to the result.  */
  CC_STATUS_INIT;
  return "and.l %#$ffff,%0\n\tdivu.w %2,%0\n\tswap %0";
}
}

static char *
output_120 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  /* The swap insn produces cc's that don't correspond to the result.  */
  CC_STATUS_INIT;
  return "divu%.w %2,%0\n\tswap %0";
}
}

static char *
output_123 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[2]) == CONST_INT
      && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
      && (DATA_REG_P (operands[0])
          || offsettable_memref_p (operands[0])))
    {
      if (GET_CODE (operands[0]) != REG)
        operands[0] = adj_offsettable_operand (operands[0], 2);
      operands[2] = gen_rtx (CONST_INT, VOIDmode,
                             INTVAL (operands[2]) & 0xffff);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      if (operands[2] == const0_rtx)
        return "clr%.w %0";
      return "and%.w %2,%0";
    }
  return "and%.l %2,%0";
}
}

static char *
output_128 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  register int logval;
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) >> 16 == 0
      && (DATA_REG_P (operands[0])
          || offsettable_memref_p (operands[0])))
    {
      if (GET_CODE (operands[0]) != REG)
        operands[0] = adj_offsettable_operand (operands[0], 2);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      return "or%.w %2,%0";
    }
  if (GET_CODE (operands[2]) == CONST_INT
      && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
      && (DATA_REG_P (operands[0])
          || offsettable_memref_p (operands[0])))
    {
      if (DATA_REG_P (operands[0]))
        {
          operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
        }
      else
        {
          operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
          operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
        }
      return "bset %1,%0";
    }
  return "or%.l %2,%0";
}
}

static char *
output_131 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[2]) >> 16 == 0
      && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
    {
      if (! DATA_REG_P (operands[0]))
        operands[0] = adj_offsettable_operand (operands[0], 2);
      /* Do not delete a following tstl %0 insn; that would be incorrect.  */
      CC_STATUS_INIT;
      return "eor%.w %2,%0";
    }
  return "eor%.l %2,%0";
}
}

static char *
output_138 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
    return "fneg%.x %1,%0";
  return "fneg%.s %f1,%0";
}
}

static char *
output_140 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
    return "fneg%.x %1,%0";
  return "fneg%.d %f1,%0";
}
}

static char *
output_142 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
    return "fabs%.x %1,%0";
  return "fabs%.s %f1,%0";
}
}

static char *
output_144 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
    return "fabs%.x %1,%0";
  return "fabs%.d %f1,%0";
}
}

static char *
output_148 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (TARGET_68020)
    return "move%.b %1,%0\n\textb%.l %0";
  return "move%.b %1,%0\n\text%.w %0\n\text%.l %0";
}
}

static char *
output_149 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (reg_mentioned_p (operands[0], operands[1]))
    return "move%.b %1,%0\n\tand%.l %#$ff,%0";
  return "clr%.l %0\n\tmove%.b %1,%0";
}
}

static char *
output_150 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[3];
  cc_status.flags |= CC_REVERSED;
  if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[1], 0) , 0);
      output_asm_insn ("cmp%.b %0,%1\n\taddq%.w %#3,%2", xoperands);
      return "";
    }
  if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[1], 0) , 0);
      output_asm_insn ("subq%.w %#3,%2\n\tcmp%.b %0,%1", xoperands);
      return "";
    }
  return "cmp%.b %0,%1";
}
}

static char *
output_151 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[3];
  if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[0], 0) , 0);
      output_asm_insn ("cmp%.b %1,%0\n\taddq%.w %#3,%2", xoperands);
      return "";
    }
  if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[0], 0) , 0);
      output_asm_insn ("subq%.w %#3,%2\n\tcmp%.b %1,%0", xoperands);
      return "";
    }
  return "cmp%.b %1,%0";
}
}

static char *
output_152 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[3];
  cc_status.flags |= CC_REVERSED;
  if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[1], 0) , 0);
      output_asm_insn ("cmp%.b %0,%1\n\taddq%.w %#3,%2", xoperands);
      return "";
    }
  if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[1], 0) , 0);
      output_asm_insn ("subq%.w %#3,%2\n\tcmp%.b %0,%1", xoperands);
      return "";
    }
  return "cmp%.b %0,%1";
}
}

static char *
output_153 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[3];
  if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[0], 0) , 0);
      output_asm_insn ("cmp%.b %1,%0\n\taddq%.w %#3,%2", xoperands);
      return "";
    }
  if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
    {
      xoperands[0] = operands[0];
      xoperands[1] = operands[1];
      xoperands[2] = XEXP (XEXP (operands[0], 0) , 0);
      output_asm_insn ("subq%.w %#3,%2\n\tcmp%.b %1,%0", xoperands);
      return "";
    }
  return "cmp%.b %1,%0";
}
}

static char *
output_154 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (INTVAL (operands[2]) == 16)
    {
      CC_STATUS_INIT;
      return "swap %0\n\tclr%.w %0";
    }
  if (INTVAL (operands[2]) == 17)
    return "swap %0\n\tclr%.w %0\n\tadd%.l %0,%0";
  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
  return "swap %0\n\tclr%.w %0\n\tasl%.l %2,%0";
}
}

static char *
output_155 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2])== 1)
    return "add%.l %0,%0";
  return "asl%.l %2,%0";
}
}

static char *
output_156 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2])== 1)
    return "add%.w %0,%0";
  return "asl%.w %2,%0";
}
}

static char *
output_157 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE(operands[2]) == CONST_INT && INTVAL(operands[2])== 1)
    return "add%.b %0,%0";
  return "asl%.b %2,%0";
}
}

static char *
output_158 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (INTVAL (operands[2]) == 16)
    return "swap %0\n\text%.l %0";
  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
  return "swap %0\n\text%.l %0\n\tasr%.l %2,%0";
}
}

static char *
output_162 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (INTVAL (operands[2]) == 16)
    {
      CC_STATUS_INIT;
      return "swap %0\n\tclr%.w %0";
    }
  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
  return "swap %0\n\tclr%.w %0\n\tlsl%.l %2,%0";
}
}

static char *
output_166 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (INTVAL (operands[2]) == 16)
    {
      CC_STATUS_INIT;
      return "clr%.w %0\n\tswap %0";
    }
  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
  return "clr%.w %0\n\tswap %0\n\tlsr%.l %2,%0";
}
}

static char *
output_176 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[0]))
    {
      if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
        return "bfins %3,%0{%b2:%b1}";
    }
  else
    operands[0]
      = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);

  if (GET_CODE (operands[3]) == MEM)
    operands[3] = adj_offsettable_operand (operands[3],
                                           (32 - INTVAL (operands[1])) / 8);
  if (INTVAL (operands[1]) == 8)
    return "move%.b %3,%0";
  return "move%.w %3,%0";
}
}

static char *
output_177 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags |= CC_NOT_NEGATIVE;
  if (REG_P (operands[1]))
    {
      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
        return "bfextu %1{%b3:%b2},%0";
    }
  else
    operands[1]
      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);

  output_asm_insn ("clr%.l %0", operands);
  if (GET_CODE (operands[0]) == MEM)
    operands[0] = adj_offsettable_operand (operands[0],
                                           (32 - INTVAL (operands[1])) / 8);
  if (INTVAL (operands[2]) == 8)
    return "move%.b %1,%0";
  return "move%.w %1,%0";
}
}

static char *
output_178 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (REG_P (operands[1]))
    {
      if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
        return "bfexts %1{%b3:%b2},%0";
    }
  else
    operands[1]
      = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);

  if (INTVAL (operands[2]) == 8)
    return "move%.b %1,%0\n\textb%.l %0";
  return "move%.w %1,%0\n\text%.l %0";
}
}

static char *
output_180 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags |= CC_NOT_NEGATIVE;
  return "bfextu %1{%b3:%b2},%0";
}
}

static char *
output_181 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  return "bfchg %0{%b2:%b1}";
}
}

static char *
output_182 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  return "bfclr %0{%b2:%b1}";
}
}

static char *
output_183 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  return "bfset %0{%b2:%b1}";
}
}

static char *
output_186 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  cc_status.flags |= CC_NOT_NEGATIVE;
  return "bfextu %1{%b3:%b2},%0";
}
}

static char *
output_187 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  return "bfclr %0{%b2:%b1}";
}
}

static char *
output_188 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  return "bfset %0{%b2:%b1}";
}
}

static char *
output_189 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
#if 0
  /* These special cases are now recognized by a specific pattern.  */
  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
    return "move%.w %3,%0";
  if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
      && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
    return "move%.b %3,%0";
#endif
  return "bfins %3,%0{%b2:%b1}";
}
}

static char *
output_190 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_191 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_192 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_193 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_194 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_195 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (operands[1] == const1_rtx
      && GET_CODE (operands[2]) == CONST_INT)
    {
      int width = GET_CODE (operands[0]) == REG ? 31 : 7;
      return output_btst (operands,
                          gen_rtx (CONST_INT, VOIDmode,
                                   width - INTVAL (operands[2])),
                          operands[0],
                          insn, 1000);
      /* Pass 1000 as SIGNPOS argument so that btst will
         not think we are testing the sign bit for an `and'
         and assume that nonzero implies a negative result.  */
    }
  if (INTVAL (operands[1]) != 32)
    cc_status.flags = CC_NOT_NEGATIVE;
  return "bftst %0{%b2:%b1}";
}
}

static char *
output_196 (operands, insn)
     rtx *operands;
     rtx insn;
{

  cc_status = cc_prev_status;
  OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0");

}

static char *
output_197 (operands, insn)
     rtx *operands;
     rtx insn;
{

  cc_status = cc_prev_status;
  OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0");

}

static char *
output_198 (operands, insn)
     rtx *operands;
     rtx insn;
{

  cc_status = cc_prev_status;
  OUTPUT_JUMP ("sgt %0", "fsgt %0", 0);

}

static char *
output_199 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     return "shi %0";
}

static char *
output_200 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0");
}

static char *
output_201 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     return "scs %0";
}

static char *
output_202 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0");
}

static char *
output_203 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     return "scc %0";
}

static char *
output_204 (operands, insn)
     rtx *operands;
     rtx insn;
{

  cc_status = cc_prev_status;
  OUTPUT_JUMP ("sle %0", "fsle %0", 0);

}

static char *
output_205 (operands, insn)
     rtx *operands;
     rtx insn;
{
 cc_status = cc_prev_status;
     return "sls %0";
}

static char *
output_206 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("beq %l0", "fbeq %l0", "beq %l0");
  else
    OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
}
}

static char *
output_207 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bne %l0", "fbne %l0", "bne %l0");
  else
    OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
}
}

static char *
output_208 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bgt %l0", "fbgt %l0", 0);
  else
    OUTPUT_JUMP ("jbgt %l0", "fbgt %l0", 0);
}
}

static char *
output_209 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bhi %l0";
  else
    return "jbhi %l0";
}
}

static char *
output_210 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("blt %l0", "fblt %l0", "bmi %l0");
  else
    OUTPUT_JUMP ("jblt %l0", "fblt %l0", "jbmi %l0");
}
}

static char *
output_211 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bcs %l0";
  else
    return "jbcs %l0";
}
}

static char *
output_212 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bge %l0", "fbge %l0", "bpl %l0");
  else
    OUTPUT_JUMP ("jbge %l0", "fbge %l0", "jbpl %l0");
}
}

static char *
output_213 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bcc %l0";
  else
    return "jbcc %l0";
}
}

static char *
output_214 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("ble %l0", "fble %l0", 0);
  else
    OUTPUT_JUMP ("jble %l0", "fble %l0", 0);
}
}

static char *
output_215 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bls %l0";
  else
    return "jbls %l0";
}
}

static char *
output_216 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bne %l0", "fbne %l0", "bne %l0");
  else
    OUTPUT_JUMP ("jbne %l0", "fbne %l0", "jbne %l0");
}
}

static char *
output_217 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("beq %l0", "fbeq %l0", "beq %l0");
  else
    OUTPUT_JUMP ("jbeq %l0", "fbeq %l0", "jbeq %l0");
}
}

static char *
output_218 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("ble %l0", "fbngt %l0", 0);
  else
    OUTPUT_JUMP ("jble %l0", "fbngt %l0", 0);
}
}

static char *
output_219 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bls %l0";
  else
    return "jbls %l0";
}
}

static char *
output_220 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bge %l0", "fbnlt %l0", "bpl %l0");
  else
    OUTPUT_JUMP ("jbge %l0", "fbnlt %l0", "jbpl %l0");
}
}

static char *
output_221 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bcc %l0";
  else
    return "jbcc %l0";
}
}

static char *
output_222 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("blt %l0", "fbnge %l0", "bmi %l0");
  else
    OUTPUT_JUMP ("jblt %l0", "fbnge %l0", "jbmi %l0");
}
}

static char *
output_223 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bcs %l0";
  else
    return "jbcs %l0";
}
}

static char *
output_224 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    OUTPUT_JUMP ("bgt %l0", "fbnle %l0", 0);
  else
    OUTPUT_JUMP ("jbgt %l0", "fbnle %l0", 0);
}
}

static char *
output_225 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bhi %l0";
  else
    return "jbhi %l0";
}
}

static char *
output_230 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (flag_all_short)
    return "bra %l0";
  else
    return "jbra %l0";
}
}

static char *
output_231 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  if (DATA_REG_P (operands[0]))
    return "dbra %0,%l1";
  if (GET_CODE (operands[0]) == MEM)
    {
      if (flag_all_short)
        return "subq%.w %#1,%0\n\tbcc %l1";
      else
        return "subq%.w %#1,%0\n\tjbcc %l1";
      }
  if (flag_all_short)
    return "subq%.w %#1,%0\n\tcmp%.w %#-1,%0\n\tbne %l1";
  else
    return "subq%.w %#1,%0\n\tcmp%.w %#-1,%0\n\tjbne %l1";
}
}

static char *
output_232 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  if (DATA_REG_P (operands[0]))
   {
     if (! REG_INIT_DBRA(operands[0]))
       if (flag_all_short)
         return "dbra %0,%l1\n\tclr.w %0\n\tsubq.l %#1,%0\n\tbcc %l1";
       else
         return "dbra %0,%l1\n\tclr.w %0\n\tsubq.l %#1,%0\n\tjbcc %l1";
     else
      {
         REG_INIT_DBRA (operands[0]) = 0;
         return "dbra %0,%l1\n\text.l %0";
      }
   }
  if (GET_CODE (operands[0]) == MEM)
    if (flag_all_short)
      return "subq.l %#1,%0\n\tbcc %l1";
    else
      return "subq.l %#1,%0\n\tjbcc %l1";
  if (ADDRESS_REG_P (operands[0]))
    if (flag_all_short)
      return "subq.w %#1,%0\n\tcmp.w %#-1,%0\n\tbne %l1";
    else
      return "subq.w %#1,%0\n\tcmp.w %#-1,%0\n\tjbne %l1";
  if (flag_all_short)
    return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tbne %l1";
  else
    return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tjbne %l1";
}
}

static char *
output_233 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  CC_STATUS_INIT;
  if (DATA_REG_P (operands[0]))
    {
      if (! REG_INIT_DBRA (operands[0]))
        if (flag_all_short)
          return "dbra %0,%l1\n\tclr.w %0\n\tsubq.l %#1,%0\n\tbcc %l1";
        else
          return "dbra %0,%l1\n\tclr.w %0\n\tsubq.l %#1,%0\n\tjbcc %l1";
    else
      {
          REG_INIT_DBRA (operands[0])=0;
          return "dbra %0,%l1\n\text.l %0";
      }
  }
  if (ADDRESS_REG_P (operands[0]))
    if (flag_all_short)
      return "subq.w %#1,%0\n\tcmp.w %#-1,%0\n\tbne %l1";
    else
      return "subq.w %#1,%0\n\tcmp.w %#-1,%0\n\tjbne %l1";
  if (flag_all_short)
    return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tbne %l1";
  else
    return "subq.l %#1,%0\n\tcmp.l %#-1,%0\n\tjbne %l1";
}
}

static char *
output_234 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF
      && ! MEM_IN_REMOTE (XEXP (operands[0],0)))
    {
      extern int flag_no_sx;
      bsr_seen=1;
      if (!flag_no_sx)
        return "SXCALL %0";
      else
        return "DOS %0";
    }
  if (flag_all_short && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
    {
      bsr_seen=1;
      if (flag_long_offset)
        return "bsr %0";
      else
        return "bsr%.w %0";
    }
  return "jbsr %0";
}
}

static char *
output_235 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF
      && ! MEM_IN_REMOTE (XEXP (operands[1],0)))
    {
      extern int flag_no_sx;
      bsr_seen=1;
      if (!flag_no_sx)
        return "SXCALL %1";
      else
        return "DOS %1";
    }
  if (flag_all_short && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
    {
      bsr_seen=1;
      if (flag_long_offset)
        return "bsr %1";
      else
        return "bsr%.w %1";
    }
  return "jbsr %1";
}
}

static char *
output_238 (operands, insn)
     rtx *operands;
     rtx insn;
{

{
  rtx xoperands[2];
  xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
  output_asm_insn ("move%.l %1,%@", xoperands);
  output_asm_insn ("move%.l %1,%-", operands);
  return "fmove%.d %+,%0";
}

}

char * const insn_template[] =
  {
    0,
    0,
    0,
    0,
    "tst%.b %0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "pea %a1",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "ext%.w %0",
    "extb%.l %0",
    0,
    0,
    0,
    "fmove%.s %f1,%0",
    0,
    "fmove%.l %1,%0",
    0,
    "fmove%.l %1,%0",
    "fmove%.w %1,%0",
    "fmove%.w %1,%0",
    "fmove%.b %1,%0",
    "fmove%.b %1,%0",
    0,
    0,
    "fmove%.b %1,%0",
    "fmove%.w %1,%0",
    "fmove%.l %1,%0",
    "fmove%.b %1,%0",
    "fmove%.w %1,%0",
    "fmove%.l %1,%0",
    0,
    0,
    "add%.w %2,%0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "sub%.w %2,%0",
    "sub%.w %2,%0",
    "sub%.w %1,%0",
    "sub%.b %2,%0",
    "sub%.b %1,%0",
    0,
    0,
    0,
    0,
    "muls%.w %2,%0",
    "muls.w %2,%0",
    "muls%.l %2,%0",
    "mulu.w %2,%0",
    "mulu.w %2,%0",
    "mulu%.l %2,%0",
    0,
    0,
    0,
    0,
    "ext.l %0\n\tdivs.w %2,%0",
    "divs.w %2,%0",
    "divs%.l %2,%0",
    "and.l %#$ffff,%0\n\tdivu.w %2,%0",
    "divu.w %2,%0",
    "divu%.l %2,%0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "divsl%.l %2,%3:%0",
    "divul%.l %2,%3:%0",
    0,
    "and%.w %2,%0",
    "and%.b %2,%0",
    "and%.w %1,%0",
    "and%.b %1,%0",
    0,
    "or%.w %2,%0",
    "or%.b %2,%0",
    0,
    "eor%.w %2,%0",
    "eor%.b %2,%0",
    "neg%.l %0",
    "neg%.w %0",
    "neg%.b %0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "not%.l %0",
    "not%.w %0",
    "not%.b %0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "asr%.l %2,%0",
    "asr%.w %2,%0",
    "asr%.b %2,%0",
    0,
    "lsl%.l %2,%0",
    "lsl%.w %2,%0",
    "lsl%.b %2,%0",
    0,
    "lsr%.l %2,%0",
    "lsr%.w %2,%0",
    "lsr%.b %2,%0",
    "rol%.l %2,%0",
    "rol%.w %2,%0",
    "rol%.b %2,%0",
    "ror%.l %2,%0",
    "ror%.w %2,%0",
    "ror%.b %2,%0",
    0,
    0,
    0,
    "bfexts %1{%b3:%b2},%0",
    0,
    0,
    0,
    0,
    "bfins %3,%0{%b2:%b1}",
    "bfexts %1{%b3:%b2},%0",
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    "jmp 2(pc,%0.w)",
    0,
    0,
    0,
    0,
    0,
    0,
    "nop",
    "lea %a1,%0",
    0,
  };

char *(*const insn_outfun[])() =
  {
    output_0,
    output_1,
    output_2,
    output_3,
    0,
    0,
    output_6,
    0,
    output_8,
    output_9,
    output_10,
    output_11,
    0,
    output_13,
    0,
    output_15,
    output_16,
    output_17,
    output_18,
    output_19,
    output_20,
    output_21,
    output_22,
    output_23,
    output_24,
    output_25,
    output_26,
    output_27,
    output_28,
    0,
    output_30,
    output_31,
    output_32,
    output_33,
    output_34,
    output_35,
    output_36,
    output_37,
    output_38,
    output_39,
    0,
    output_41,
    output_42,
    output_43,
    output_44,
    0,
    0,
    0,
    output_48,
    output_49,
    output_50,
    output_51,
    0,
    0,
    0,
    output_55,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    output_66,
    output_67,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    output_75,
    0,
    output_77,
    output_78,
    output_79,
    output_80,
    output_81,
    output_82,
    0,
    output_84,
    0,
    output_86,
    output_87,
    0,
    0,
    0,
    0,
    0,
    0,
    output_94,
    0,
    output_96,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    output_104,
    0,
    output_106,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    output_114,
    0,
    output_116,
    output_117,
    output_118,
    output_119,
    output_120,
    0,
    0,
    output_123,
    0,
    0,
    0,
    0,
    output_128,
    0,
    0,
    output_131,
    0,
    0,
    0,
    0,
    0,
    0,
    output_138,
    0,
    output_140,
    0,
    output_142,
    0,
    output_144,
    0,
    0,
    0,
    output_148,
    output_149,
    output_150,
    output_151,
    output_152,
    output_153,
    output_154,
    output_155,
    output_156,
    output_157,
    output_158,
    0,
    0,
    0,
    output_162,
    0,
    0,
    0,
    output_166,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    output_176,
    output_177,
    output_178,
    0,
    output_180,
    output_181,
    output_182,
    output_183,
    0,
    0,
    output_186,
    output_187,
    output_188,
    output_189,
    output_190,
    output_191,
    output_192,
    output_193,
    output_194,
    output_195,
    output_196,
    output_197,
    output_198,
    output_199,
    output_200,
    output_201,
    output_202,
    output_203,
    output_204,
    output_205,
    output_206,
    output_207,
    output_208,
    output_209,
    output_210,
    output_211,
    output_212,
    output_213,
    output_214,
    output_215,
    output_216,
    output_217,
    output_218,
    output_219,
    output_220,
    output_221,
    output_222,
    output_223,
    output_224,
    output_225,
    0,
    0,
    0,
    0,
    output_230,
    output_231,
    output_232,
    output_233,
    output_234,
    output_235,
    0,
    0,
    output_238,
  };

rtx (*const insn_gen_function[]) () =
  {
    0,
    0,
    gen_tstsi,
    gen_tsthi,
    gen_tstqi,
    gen_tstsf,
    0,
    gen_tstdf,
    0,
    gen_cmpsi,
    gen_cmphi,
    gen_cmpqi,
    gen_cmpdf,
    0,
    gen_cmpsf,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    gen_movsi,
    0,
    0,
    gen_movhi,
    gen_movstricthi,
    0,
    gen_movqi,
    gen_movstrictqi,
    gen_movsf,
    gen_movdf,
    gen_movdi,
    gen_pushasi,
    0,
    gen_truncsiqi2,
    gen_trunchiqi2,
    gen_truncsihi2,
    gen_zero_extendhisi2,
    gen_zero_extendqihi2,
    gen_zero_extendqisi2,
    0,
    0,
    0,
    gen_extendhisi2,
    gen_extendqihi2,
    gen_extendqisi2,
    gen_extendsfdf2,
    0,
    gen_truncdfsf2,
    0,
    gen_floatsisf2,
    0,
    gen_floatsidf2,
    0,
    gen_floathisf2,
    gen_floathidf2,
    gen_floatqisf2,
    gen_floatqidf2,
    gen_ftruncdf2,
    gen_ftruncsf2,
    gen_fixsfqi2,
    gen_fixsfhi2,
    gen_fixsfsi2,
    gen_fixdfqi2,
    gen_fixdfhi2,
    gen_fixdfsi2,
    gen_addsi3,
    0,
    0,
    gen_addhi3,
    0,
    0,
    gen_addqi3,
    0,
    0,
    gen_adddf3,
    0,
    gen_addsf3,
    0,
    gen_subsi3,
    0,
    gen_subhi3,
    0,
    gen_subqi3,
    0,
    gen_subdf3,
    0,
    gen_subsf3,
    0,
    gen_mulhi3,
    gen_mulhisi3,
    gen_mulsi3,
    gen_umulhi3,
    gen_umulhisi3,
    gen_umulsi3,
    gen_muldf3,
    0,
    gen_mulsf3,
    0,
    gen_divhi3,
    gen_divhisi3,
    gen_divsi3,
    gen_udivhi3,
    gen_udivhisi3,
    gen_udivsi3,
    gen_divdf3,
    0,
    gen_divsf3,
    0,
    gen_modhi3,
    gen_modhisi3,
    gen_umodhi3,
    gen_umodhisi3,
    gen_divmodsi4,
    gen_udivmodsi4,
    gen_andsi3,
    gen_andhi3,
    gen_andqi3,
    0,
    0,
    gen_iorsi3,
    gen_iorhi3,
    gen_iorqi3,
    gen_xorsi3,
    gen_xorhi3,
    gen_xorqi3,
    gen_negsi2,
    gen_neghi2,
    gen_negqi2,
    gen_negsf2,
    0,
    gen_negdf2,
    0,
    gen_abssf2,
    0,
    gen_absdf2,
    0,
    gen_one_cmplsi2,
    gen_one_cmplhi2,
    gen_one_cmplqi2,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    gen_ashlsi3,
    gen_ashlhi3,
    gen_ashlqi3,
    0,
    gen_ashrsi3,
    gen_ashrhi3,
    gen_ashrqi3,
    0,
    gen_lshlsi3,
    gen_lshlhi3,
    gen_lshlqi3,
    0,
    gen_lshrsi3,
    gen_lshrhi3,
    gen_lshrqi3,
    gen_rotlsi3,
    gen_rotlhi3,
    gen_rotlqi3,
    gen_rotrsi3,
    gen_rotrhi3,
    gen_rotrqi3,
    0,
    0,
    0,
    gen_extv,
    gen_extzv,
    0,
    0,
    0,
    gen_insv,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    gen_seq,
    gen_sne,
    gen_sgt,
    gen_sgtu,
    gen_slt,
    gen_sltu,
    gen_sge,
    gen_sgeu,
    gen_sle,
    gen_sleu,
    gen_beq,
    gen_bne,
    gen_bgt,
    gen_bgtu,
    gen_blt,
    gen_bltu,
    gen_bge,
    gen_bgeu,
    gen_ble,
    gen_bleu,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    gen_casesi_1,
    gen_casesi_2,
    gen_casesi,
    0,
    gen_jump,
    0,
    0,
    0,
    gen_call,
    gen_call_value,
    gen_nop,
    0,
    0,
  };

const short insn_n_operands[] =
  {
    2,
    2,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    1,
    2,
    2,
    1,
    3,
    2,
    2,
    2,
    3,
    2,
    2,
    3,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    3,
    3,
    3,
    3,
    2,
    2,
    3,
    2,
    2,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    2,
    3,
    2,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    4,
    4,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    2,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    3,
    4,
    4,
    4,
    4,
    4,
    4,
    3,
    3,
    4,
    4,
    4,
    3,
    3,
    4,
    3,
    3,
    3,
    3,
    3,
    3,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    4,
    2,
    5,
    1,
    0,
    1,
    1,
    1,
    2,
    3,
    0,
    2,
    2,
  };

const short insn_n_dups[] =
  {
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    1,
    1,
    0,
    1,
    1,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    1,
    0,
    1,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    2,
    2,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    3,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    2,
    2,
    2,
    0,
    0,
    0,
    0,
    0,
  };

char *const insn_operand_constraint[][MAX_RECOG_OPERANDS] =
  {
    { "=m", "rm<>fyF", },
    { "=m", "rm<>Fy", },
    { "rm", },
    { "rm", },
    { "dm", },
    { "", },
    { "fdm", },
    { "", },
    { "fm", },
    { "rKs,mr,>", "mr,Ksr,>", },
    { "rnm,d,n,m", "d,rnm,m,n", },
    { "dn,md,>", "dm,nd,>", },
    { "", "", },
    { "f,mG", "fmG,f", },
    { "", "", },
    { "f,mdG", "fmdG,f", },
    { "do", "di", },
    { "d", "di", },
    { "do", "d", },
    { "d", "d", },
    { "md", "i", },
    { "o,d", "i,i", },
    { "do", "i", },
    { "dm", },
    { "dm", "i", },
    { "=m", "J", },
    { "=g", },
    { "=r", "m", "m", },
    { "=a", "i", },
    { "", "", },
    { "=g,da,y,!*x*r*m", "daymKs,i,g,*x*r*m", },
    { "=r", "m", "m", },
    { "=g", "g", },
    { "+dm", "rmn", },
    { "=r", "m", "m", },
    { "=d,*a,m,m,?*a", "dmi*a,d*a,dmi,?*a,m", },
    { "+dm", "dmn", },
    { "=rmf,x,y,rm,!x,!rm", "rmfF,xH,rmF,y,rm,x", },
    { "=rm,&rf,&rof<>,y,rm,x,!x,!rm", "rf,m,rofF<>,rmF,y,xH,rm,x", },
    { "=rm,&r,&ro<>,y,rm,!*x,!rm", "rF,m,roi<>F,rmiF,y,rmF,*x", },
    { "=m", "p", },
    { "=a", "p", },
    { "=dm,d", "doJ,i", },
    { "=dm,d", "doJ,i", },
    { "=dm,d", "roJ,i", },
    { "", "", },
    { "", "", },
    { "", "", },
    { "=do<>", "rmn", },
    { "=do<>", "dmn", },
    { "=do<>", "dmn", },
    { "=*d,a", "0,rmn", },
    { "=d", "0", },
    { "=d", "0", },
    { "", "", },
    { "=*fdm,f", "f,dmF", },
    { "", "", },
    { "=dm", "f", },
    { "", "", },
    { "=f", "dmi", },
    { "", "", },
    { "=f", "dmi", },
    { "=f", "dmn", },
    { "=f", "dmn", },
    { "=f", "dmn", },
    { "=f", "dmn", },
    { "=f", "fFm", },
    { "=f", "dfFm", },
    { "=dm", "f", },
    { "=dm", "f", },
    { "=dm", "f", },
    { "=dm", "f", },
    { "=dm", "f", },
    { "=dm", "f", },
    { "", "", "", },
    { "=m,r,!a,!a", "%0,0,a,rJK", "dIKLs,mrIKLs,rJK,a", },
    { "=a", "0", "rmn", },
    { "=m,r", "%0,0", "dn,rmn", },
    { "+m,d", "dn,rmn", },
    { "+m,d", "dn,rmn", },
    { "=m,d", "%0,0", "dn,dmn", },
    { "+m,d", "dn,dmn", },
    { "+m,d", "dn,dmn", },
    { "", "", "", },
    { "=f", "%0", "fmG", },
    { "", "", "", },
    { "=f", "%0", "fdmF", },
    { "=m,r,!a,?d", "0,0,a,mrIKs", "dIKs,mrIKs,J,0", },
    { "=a", "0", "rmn", },
    { "=m,r", "0,0", "dn,rmn", },
    { "+m,d", "dn,rmn", },
    { "=m,d", "0,0", "dn,dmn", },
    { "+m,d", "dn,dmn", },
    { "", "", "", },
    { "=f", "0", "fmG", },
    { "", "", "", },
    { "=f", "0", "fdmF", },
    { "=d", "%0", "dmn", },
    { "=d", "%0", "dmn", },
    { "=d", "%0", "dmsK", },
    { "=d", "%0", "dmn", },
    { "=d", "%0", "dmn", },
    { "=d", "%0", "dmsK", },
    { "", "", "", },
    { "=f", "%0", "fmG", },
    { "", "", "", },
    { "=f", "%0", "fdmF", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmsK", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmsK", },
    { "", "", "", },
    { "=f", "0", "fmG", },
    { "", "", "", },
    { "=f", "0", "fdmF", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmn", },
    { "=d", "0", "dmsK", "=d", },
    { "=d", "0", "dmsK", "=d", },
    { "=m,d", "%0,0", "dKs,dmKs", },
    { "=m,d", "%0,0", "dn,dmn", },
    { "=m,d", "%0,0", "dn,dmn", },
    { "=d", "dm", "0", },
    { "=d", "dm", "0", },
    { "=m,d", "%0,0", "dKs,dmKs", },
    { "=m,d", "%0,0", "dn,dmn", },
    { "=m,d", "%0,0", "dn,dmn", },
    { "=do,m", "%0,0", "di,dKs", },
    { "=dm", "%0", "dn", },
    { "=dm", "%0", "dn", },
    { "=dm", "0", },
    { "=dm", "0", },
    { "=dm", "0", },
    { "", "", },
    { "=f", "fdmF", },
    { "", "", },
    { "=f", "fmF", },
    { "", "", },
    { "=f", "fdmF", },
    { "", "", },
    { "=f", "fmF", },
    { "=dm", "0", },
    { "=dm", "0", },
    { "=dm", "0", },
    { "=d", "m", },
    { "=d", "m", },
    { "i", "m", },
    { "m", "i", },
    { "i", "m", },
    { "m", "i", },
    { "=d", "0", "i", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "i", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "i", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "i", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "=d", "0", "dI", },
    { "+do", "i", "i", "d", },
    { "=&d", "do", "i", "i", },
    { "=d", "do", "i", "i", },
    { "=d,d", "o,d", "di,di", "di,di", },
    { "=d,d", "o,d", "di,di", "di,di", },
    { "+o,d", "di,di", "di,di", "i,i", },
    { "+o,d", "di,di", "di,di", },
    { "+o,d", "di,di", "di,di", },
    { "+o,d", "di,di", "di,di", "d,d", },
    { "=d", "d", "di", "di", },
    { "=d", "d", "di", "di", },
    { "+d", "di", "di", },
    { "+d", "di", "di", },
    { "+d", "di", "di", "d", },
    { "o", "di", "di", },
    { "o", "di", "di", },
    { "o", "di", "di", },
    { "d", "di", "di", },
    { "d", "di", "di", },
    { "d", "di", "di", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { "=d", },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { "", "", "", "", },
    { "", "", },
    { "", "", "", "", "", },
    { "r", },
    { 0 },
    { "=g", },
    { "=g", },
    { "=g", },
    { "o", "g", },
    { "=rf", "o", "g", },
    { 0 },
    { "=a", "p", },
    { "f", "ad", },
  };

const enum machine_mode insn_operand_mode[][MAX_RECOG_OPERANDS] =
  {
    { DFmode, DFmode, },
    { DImode, DImode, },
    { SImode, },
    { HImode, },
    { QImode, },
    { SFmode, },
    { SFmode, },
    { DFmode, },
    { DFmode, },
    { SImode, SImode, },
    { HImode, HImode, },
    { QImode, QImode, },
    { DFmode, DFmode, },
    { DFmode, DFmode, },
    { SFmode, SFmode, },
    { SFmode, SFmode, },
    { QImode, SImode, },
    { SImode, SImode, },
    { QImode, SImode, },
    { SImode, SImode, },
    { QImode, SImode, },
    { HImode, SImode, },
    { SImode, SImode, },
    { QImode, },
    { QImode, SImode, },
    { SImode, SImode, },
    { SImode, },
    { VOIDmode, VOIDmode, VOIDmode, },
    { SImode, SImode, },
    { SImode, SImode, },
    { SImode, SImode, },
    { VOIDmode, VOIDmode, VOIDmode, },
    { HImode, HImode, },
    { HImode, HImode, },
    { VOIDmode, VOIDmode, VOIDmode, },
    { QImode, QImode, },
    { QImode, QImode, },
    { SFmode, SFmode, },
    { DFmode, DFmode, },
    { DImode, DImode, },
    { SImode, SImode, },
    { SImode, SImode, },
    { QImode, SImode, },
    { QImode, HImode, },
    { HImode, SImode, },
    { SImode, HImode, },
    { HImode, QImode, },
    { SImode, QImode, },
    { SImode, HImode, },
    { HImode, QImode, },
    { SImode, QImode, },
    { SImode, HImode, },
    { HImode, QImode, },
    { SImode, QImode, },
    { DFmode, SFmode, },
    { DFmode, SFmode, },
    { SFmode, DFmode, },
    { SFmode, DFmode, },
    { SFmode, SImode, },
    { SFmode, SImode, },
    { DFmode, SImode, },
    { DFmode, SImode, },
    { SFmode, HImode, },
    { DFmode, HImode, },
    { SFmode, QImode, },
    { DFmode, QImode, },
    { DFmode, DFmode, },
    { SFmode, SFmode, },
    { QImode, SFmode, },
    { HImode, SFmode, },
    { SImode, SFmode, },
    { QImode, DFmode, },
    { HImode, DFmode, },
    { SImode, DFmode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, HImode, },
    { HImode, HImode, HImode, },
    { HImode, HImode, },
    { HImode, HImode, },
    { QImode, QImode, QImode, },
    { QImode, QImode, },
    { QImode, QImode, },
    { DFmode, DFmode, DFmode, },
    { DFmode, DFmode, DFmode, },
    { SFmode, SFmode, SFmode, },
    { SFmode, SFmode, SFmode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, HImode, },
    { HImode, HImode, HImode, },
    { HImode, HImode, },
    { QImode, QImode, QImode, },
    { QImode, QImode, },
    { DFmode, DFmode, DFmode, },
    { DFmode, DFmode, DFmode, },
    { SFmode, SFmode, SFmode, },
    { SFmode, SFmode, SFmode, },
    { HImode, HImode, HImode, },
    { SImode, HImode, HImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { SImode, HImode, HImode, },
    { SImode, SImode, SImode, },
    { DFmode, DFmode, DFmode, },
    { DFmode, DFmode, DFmode, },
    { SFmode, SFmode, SFmode, },
    { SFmode, SFmode, SFmode, },
    { HImode, HImode, HImode, },
    { HImode, SImode, HImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { HImode, SImode, HImode, },
    { SImode, SImode, SImode, },
    { DFmode, DFmode, DFmode, },
    { DFmode, DFmode, DFmode, },
    { SFmode, SFmode, SFmode, },
    { SFmode, SFmode, SFmode, },
    { HImode, HImode, HImode, },
    { HImode, SImode, HImode, },
    { HImode, HImode, HImode, },
    { HImode, SImode, HImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, HImode, SImode, },
    { SImode, QImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, },
    { HImode, HImode, },
    { QImode, QImode, },
    { SFmode, SFmode, },
    { SFmode, SFmode, },
    { DFmode, DFmode, },
    { DFmode, DFmode, },
    { SFmode, SFmode, },
    { SFmode, SFmode, },
    { DFmode, DFmode, },
    { DFmode, DFmode, },
    { SImode, SImode, },
    { HImode, HImode, },
    { QImode, QImode, },
    { SImode, SImode, },
    { SImode, SImode, },
    { QImode, SImode, },
    { SImode, QImode, },
    { QImode, SImode, },
    { SImode, QImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, },
    { HImode, HImode, HImode, },
    { QImode, QImode, QImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, QImode, SImode, SImode, },
    { SImode, QImode, SImode, SImode, },
    { QImode, SImode, SImode, VOIDmode, },
    { QImode, SImode, SImode, },
    { QImode, SImode, SImode, },
    { QImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, SImode, },
    { QImode, SImode, SImode, },
    { QImode, SImode, SImode, },
    { QImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { SImode, SImode, SImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { QImode, },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { VOIDmode },
    { SImode, SImode, SImode, SImode, },
    { SImode, SImode, },
    { SImode, SImode, SImode, VOIDmode, VOIDmode, },
    { HImode, },
    { VOIDmode },
    { HImode, },
    { SImode, },
    { SImode, },
    { QImode, SImode, },
    { VOIDmode, QImode, SImode, },
    { VOIDmode },
    { SImode, QImode, },
    { VOIDmode, VOIDmode, },
  };

const char insn_operand_strict_low[][MAX_RECOG_OPERANDS] =
  {
    { 0, 0, },
    { 0, 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, },
    { 0, 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, 0, },
    { 0, 0, },
    { 1, 0, },
    { 0, 0, 0, },
    { 0, 0, },
    { 1, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 1, 0, },
    { 1, 0, },
    { 0, 0, 0, },
    { 1, 0, },
    { 1, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 1, 0, },
    { 0, 0, 0, },
    { 1, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, 0, 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0, },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0, 0, 0, 0, },
    { 0, 0, },
    { 0, 0, 0, 0, 0, },
    { 0, },
    { 0 },
    { 0, },
    { 0, },
    { 0, },
    { 0, 0, },
    { 0, 0, 0, },
    { 0 },
    { 0, 0, },
    { 0, 0, },
  };

int (*const insn_operand_predicate[][MAX_RECOG_OPERANDS])() =
  {
    { push_operand, general_operand, },
    { push_operand, general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, general_operand, },
    { nonimmediate_operand, },
    { nonimmediate_operand, general_operand, },
    { push_operand, general_operand, },
    { x68k_test_operand, },
    { 0, 0, 0, },
    { register_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { 0, 0, 0, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { 0, 0, 0, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { push_operand, address_operand, },
    { register_operand, address_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { register_operand, general_operand, },
    { register_operand, general_operand, },
    { register_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, general_operand, },
    { general_operand, memory_operand, },
    { general_operand, memory_operand, },
    { general_operand, memory_operand, },
    { memory_operand, general_operand, },
    { general_operand, memory_operand, },
    { memory_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { general_operand, general_operand, general_operand, },
    { nonimmediate_operand, immediate_operand, immediate_operand, general_operand, },
    { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, },
    { general_operand, nonimmediate_operand, immediate_operand, immediate_operand, },
    { general_operand, nonimmediate_operand, general_operand, general_operand, },
    { general_operand, nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, immediate_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, general_operand, },
    { general_operand, nonimmediate_operand, general_operand, general_operand, },
    { general_operand, nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, general_operand, },
    { memory_operand, general_operand, general_operand, },
    { memory_operand, general_operand, general_operand, },
    { memory_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { nonimmediate_operand, general_operand, general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { 0 },
    { general_operand, immediate_operand, general_operand, general_operand, },
    { 0, 0, },
    { general_operand, immediate_operand, general_operand, 0, 0, },
    { general_operand, },
    { 0 },
    { general_operand, },
    { general_operand, },
    { general_operand, },
    { general_operand, general_operand, },
    { 0, general_operand, general_operand, },
    { 0 },
    { general_operand, address_operand, },
    { 0, 0, },
  };

#ifndef DEFAULT_MACHINE_INFO
#define DEFAULT_MACHINE_INFO 0
#endif

const INSN_MACHINE_INFO insn_machine_info[] =
  {
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
     { DEFAULT_MACHINE_INFO },
  };

const short insn_n_alternatives[] =
  {
    1,
    1,
    1,
    1,
    1,
     0,
    1,
     0,
    1,
    3,
    4,
    3,
     0,
    2,
     0,
    2,
    1,
    1,
    1,
    1,
    1,
    2,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
     0,
    4,
    1,
    1,
    1,
    1,
    5,
    1,
    6,
    8,
    7,
    1,
    1,
    2,
    2,
    2,
     0,
     0,
     0,
    1,
    1,
    1,
    2,
    1,
    1,
     0,
    2,
     0,
    1,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
     0,
    4,
    1,
    2,
    2,
    2,
    2,
    2,
    2,
     0,
    1,
     0,
    1,
    4,
    1,
    2,
    2,
    2,
    2,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    2,
    2,
    2,
    1,
    1,
    2,
    2,
    2,
    2,
    1,
    1,
    1,
    1,
    1,
     0,
    1,
     0,
    1,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    2,
    2,
    2,
    2,
    2,
    2,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
    1,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
     0,
    1,
     0,
    1,
    1,
    1,
    1,
    1,
     0,
    1,
    1,
  };

